The present invention generally relates to fabrication of semiconductor devices and more particularly to fabrication and construction of a high speed field-effect transistor.
High-speed logic integrated circuits generally use high-speed CMOS circuits. CMOS circuits consume little electric power and are particularly suited for this purpose. In order to increase the operational speed of high-speed CMOS circuits further, a very fast field-effect transistor is needed.
Conventionally, the operational speed of a field-effect transistor has been increased mainly by reducing the gate length, which in turn is achieved by a device miniaturization. For example, MOS transistors having a gate length as small as 0.35 μm, are used these days for such high performance applications.
On the other hand, further reduction of gate length is generally difficult in MOS transistors, as carriers tend to experience excessive acceleration in a channel region immediately under a gate electrode of the MOS transistor when the gate length of the MOS transistor is thus reduced. The carriers thus accelerated tend to penetrate into a gate oxide film and form fixed electric charges therein, while such fixed electric charges tend to modify the threshold characteristics of the MOS transistor.
In more detail, the carriers thus penetrated into the gate oxide film enter the SiO2 structure that form the gate oxide film, wherein the carriers thus penetrated into the SiO2 structure are held stably when the carriers are captured by the dangling bonds of the SiO2 structure.
Thus, it has been practiced conventionally in the art of MOS transistors to terminate any dangling bonds existing in the gate oxide film by introducing N atoms thereinto, so that the number of the sites which may capture the carriers is reduced as much as possible.
FIGS. 1A–1D show a conventional fabrication process of a MOS transistor.
Referring to FIG. 1A, a field oxide film 2 is formed on a Si substrate 1 doped to the p-type or n-type, such that the field oxide film 2 defines a device region 1A on the surface of the substrate 1. The field oxide film 2 is typically formed by a wet etching process with a thickness of 300–400 nm. Further, a thermal oxide film 3 is formed on the Si substrate 1 so as to cover the device region 1A with a thickness of typically about 6 nm. The thermal oxide film 3 acts as a gate oxide film of the MOS transistor to be formed.
The structure of FIG. 1A is then annealed in an N2O atmosphere at a temperature of typically 800° C., such that N atoms in the atmosphere are incorporated into the gate oxide film 3.
Next, in the step of FIG. 1B, a polysilicon film 4 is deposited on the structure of FIG. 1A by a CVD process conducted at a temperature of 800–900° C., typically with a thickness of about 150 nm. Further, the polysilicon film 4 is patterned in the step of FIG. 1C by an anisotropic etching process such as an RIE (reactive ion etching) process, and a gate electrode 4A is formed as a result.
After the gate electrode 4A is thus formed, an ion implantation process of a p-type dopant such as B or an n-type dopant such as As or P is introduced into the substrate 1 while using the gate electrode 4A as a mask. Thereby, diffusion regions 1B and 1C are formed in the substrate 1 respectively in correspondence to a source region and a drain region of the MOS transistor to be formed. Further, a CVD-SiO2 film 5 is deposited on the structure thus obtained by a CVD process conducted at the temperature of 800–900° C., typically with a thickness of about 100 nm.
Next, in the step of FIG. 1D, the CVD-SiO2 film 5 is subjected to an anisotropic etching process that acts substantially vertically to the principal surface of the substrate 1, and side wall oxides 5A and 5B are formed at respective lateral sides of the gate electrode 4A. Further, by carrying out the ion implantation process of the p-type dopant or the n-type dopant once more into the substrate 1 in the state that the gate electrode 4A carries the side wall oxides 5A and 5B, further diffusion regions 1B′ and 1C′ having a higher dopant level are formed inside the diffusion regions 1B and 1C. In other words, the MOS transistor thus formed has a so-called LDD (lightly doped drain) structure.
It should be noted that, in the MOS transistor of the foregoing structure, the gate oxide film 3 acts as an etching stopper when patterning the gate electrode 4A. Thereby, the part of the gate oxide film 3 not protected by the gate electrode 4A may experience an increased degree of damage during the etching process. For example, the Si—O bonds in the SiO2 structure of the gate oxide film 3 may be broken.
When such breaking of the Si—O bond occurs, dangling bonds are formed inevitably in the structure of the gate oxide film 3, while it is known that the dangling bonds tend to capture H or OH ions. In the case of the high speed MOS transistor of FIG. 1D that has a short channel length, there is a substantial risk that the dangling bonds in the gate oxide film 3 capture the hot carriers that are accelerated at the edge of drain region 1C and penetrated into the gate oxide film 3 as indicated in FIG. 2, wherein FIG. 2 shows the drain region 1C in an enlarged scale.
In order to overcome the problem, it has been proposed to introduce N atoms into the gate oxide film 3 in the process of FIG. 1A, such that the N atoms thus introduced terminate the dangling bonds in the gate oxide film 3. As a result of such a process, the trapping of the hot electrons by the dangling bonds is reduced substantially.
On the other hand, the conventional process of FIGS. 1A–1D raises a problem in that, because the N atoms are introduced at a relatively early phase of the process, the N atoms thus incorporated easily escape in the following processes, particularly those including thermal annealing processes. In other words, it has been necessary in the conventional process of FIGS. 1A–1D to incorporate a very large amount of N atoms into the gate oxide film 3 in order that such a doping by the N atoms is effective for suppressing the trapping of the hot carriers by the dangling bonds.
When the N atoms are introduced in the step of FIG. 1A, it should be noted that the N atoms are introduced not only into the part of the gate oxide film 3 corresponding to the edge part of the drain region as shown in FIG. 2 but also into the part immediately underneath the gate electrode 4A. Thereby, the MOS transistor thus obtained tends to show a threshold characteristic substantially different from the desired or designed threshold characteristic.
FIGS. 3A and 3B show a flat-band voltage VFB and a threshold voltage VTH of the MOS transistor for the case in which the gate oxide film, formed as a result of a thermal oxidation process in a dry O2 environment, is exposed to various N-containing atmospheres at a temperature of about 800° C.
Referring to FIGS. 3A and 3B, it will be noted that both the VFB and the VTH are modified significantly as a result of the thermal annealing process conducted in the NO or N2O atmospheres for various durations. As already noted, the concentration of the N atoms in the gate oxide film 3 is changed substantially by the heating processes included in the steps of FIGS. 1A–1D. Thus, it has been difficult in the conventional MOS transistor, fabricated according to the process of FIGS. 1A–1D, to control the characteristics thereof exactly, and there has been a problem in that the transistor shows a large scattering of the characteristics. This problem becomes particularly acute in the MOS transistors in which a very large amount of N atoms are introduced into the gate oxide film for effective termination of the dangling bonds therein.